While algorithmic improvements will allow Deep Learning to evolve, much hinges on hardware’s ability to keep delivering ever higher performance and data processing storage and processing capability.
This invention is a set of techniques that are valued-based methods for reducing the number of computations that need to be performed when executing Deep Learning Algorithms and do not require intervention from the Machine Learning expert.
By exploiting ineffectual computations, weight sparsity, precision variability, and bit content, the accelerator designs transparently reduce the amount of work that needs to be performed by neural networks. The methods lead to the design of performance-, energy-, and/or cost-optimized computing engines for various applications domains.
All work with out-of-the-box Deep Learning networks and rely on value properties exhibited by typical models such as value- and bit-sparsity and data type need variability, and reward model optimizations.
Deep learning (DL), a subset of artificial intelligence (AI), is transforming our world. DL architectures such as neural networks have been applied to fields including computer vision, speech recognition, natural language processing, audio recognition, bioinformatics, and drug design.
- The proprietary, value-based architectures deliver two to three orders of magnitude faster data processing and energy efficiency without requiring alterations to existing hardware
The most important characteristic of our technology is that not only it delivers benefits today without requiring any changes to applications, it also provides strong incentives for Deep Learning developers to advance the state-of-the-art in techniques that are only partially successful today such as precision reduction, or different number representations. This is because our techniques deliver gradual benefits for gradual advances without having to redesign and redeploy hardware.